L1M1TL355 CPU Instruction Set Architecture

Reference documentation for my custom instruction set.

The content for this architecture includes immediate and register to register storage, immediate and register arithmetic, as well as a set of branch instructions.

1. Store Immediate Value

Assembly: Store[IMM] (Register, Number)

FieldBitsDescription
Opcode00000—
Register5Destination register
Number2121-bit immediate value
Write_en1Write enable
Loads a number into a register.

2. Arithmetic with Immediate

Assembly: Arith[IMM, type] (Register, Number)

FieldBitsDescription
Opcode00001—
Register5Target register
Switch3Operation code
Numerical13Immediate value
Compare Switch3Change the compare subtype
Borrow/Carry1Carry-in or borrow-in
Write Enable1—

Operations (Switch)

  • ADD — Arith[IMM, ADD] (Reg, Num, Carry) — 000
  • SUB — Arith[IMM, SUB] (Reg, Num, Borrow) — 001
  • COM — Arith[IMM, COM] (Reg, Num, Comp_Switch) — 010
  • LFT — Arith[IMM, LFT] (Reg, Num) — 011
  • RGT — Arith[IMM, RGT] (Reg, Num) — 100
  • AND — Arith[IMM, AND] (Reg, Num) — 101
  • LOR — Arith[IMM, LOR] (Reg, Num) — 110
  • XOR — Arith[IMM, XOR] (Reg, Num) — 111
Condition outputs all 1s if the condition is met.

The conditions are:
  • LOW — below — [0, 000]
  • ABV — above — [0, 001]
  • EQL — equal — [0, 010]
  • ZRO — zero — [0, 011]
  • NLO — not low — [1, 000]
  • NAB — not above — [1, 001]
  • NEQ — not equal — [1, 010]
  • NZR — not zero — [1, 011]
  • UNC — unconditional — [0, 100]

3. Register Store

Assembly: Store[REG] (R1, R2, Switch) or Store[OUT]

FieldBitsDescription
Opcode00010—
Register15Source
Register25Destination if REG, not used if OUT
Write Enable1—
Switch150 = reg store, 1 - 14 = out (encoded for 15-bit addressing out from pins)
  • Switch 0 — Move / store between registers
  • Switch 1 — Store[OUT] — Output/special store

4. Register Arithmetic

Assembly: Arith[REG, type] (R1, R2)

FieldBitsDescription
Opcode00011—
Register5Left Operand
Switch3Operation
Register 25Right Operand
Carry/Borrow1For Addition/Subtraction
Write Enable1—
Compare Switch3Change the compare subtype
Unused9—

Operations (Switch)

  • Add — Arith[REG, ADD] (R1, R2, Carry) — 000
  • Sub — Arith[REG, SUB] (R1, R2, Borrow) — 001
  • Compare — Arith[REG, COM] (R1, R2) — 010
  • Left Shift — Arith[REG, LFT] (R1, R2) — 011
  • Right Shift — Arith[REG, RGT] (R1, R2) — 100
  • Logical AND — Arith[REG, AND] (R1, R2) — 101
  • Logical OR — Arith[REG, LOR] (R1, R2) — 110
  • Logical XOR — Arith[REG, XOR] (R1, R2) — 111
Condition outputs all 1s if the condition is met.

The conditions are:
  • LOW — below — [0, 000]
  • ABV — above — [0, 001]
  • EQL — equal — [0, 010]
  • ZRO — zero — [0, 011]
  • NLO — not low — [1, 000]
  • NAB — not above — [1, 001]
  • NEQ — not equal — [1, 010]
  • NZR — not zero — [1, 011]
  • UNC — unconditional — [0, 100]

5. Compare Jump

Assembly: Jump[R] (R1, R2)

FieldBitsDescription
Opcode00100—
Condition Register5If all bits 1, jump
Location Register5Jump target address register
Unused17—